1. Field of the Invention
The present invention relates to a method of optimizing measurement conditions of an overlay metrology system and a method of optimizing an alignment mark shape or an alignment mark measuring system in an aligner.
2. Description of the Related Art
Overlay metrology systems are used to determine whether or not elements of semiconductor devices and LCD (liquid crystal display) devices are properly overlaid each other or whether the pattern formed in accordance with the under layer is deviated from the under layer when semiconductor devices and LCD devices are manufactured, for example. As the overlay metrology system, scanning electron microscope (SEM) type overlay metrology systems and optical type overlay metrology systems are now commercially available on the market. FIG. 1 of the accompanying drawings shows an outline of the optical type overlay metrology system.
Standards of accuracy of conventional overlay metrology system are a measurement reproducibility (3.sigma.) and TIS (Tool-Induced-Shift).
The measurement reproducibility (3.sigma.) can be obtained by calculating fluctuations of measured values of overlay accuracy relative to the same measurement mark after overlay accuracy had been sequentially measured at a plurality of measuring marks formed on a substrate and the measurement had been repeated a plurality of times. Incidentally, .sigma. represents a fluctuation (standard deviation) of measured values of overlay accuracy relative to the same measurement mark. If 3.sigma. is larger, measured values are fluctuated even though the same measurement mark is measured. That is to say, accuracy of the overlay metrology system is low.
TIS is defined as follows. Position coordinates of a plurality of measurement marks formed on the substrate are measured sequentially. Then, the substrate is rotated 180 degrees and position coordinates of a plurality of measurement marks formed again on the substrate are measured sequentially. Assuming that X coordinate and Y coordinate of a certain measurement mark provided before the substrate is rotated are X.sub.0 and Y.sub.0 and that X coordinate and Y coordinate of the above-mentioned measurement mark provided after the substrate was rotated 180 degrees are X.sub.180 and Y.sub.180, then in the same measurement mark, we have: EQU X.sub.0 =-X.sub.180 EQU Y.sub.0 =-Y.sub.180
However, the aforesaid equalities are not established in actual practice but we have: EQU X.sub.0 -X.sub.180 EQU Y.sub.0 -Y.sub.180
Mean value of X.sub.0 and X.sub.180 and mean value of Y.sub.0 and Y.sub.180 are referred to as TIS. The TIS is an index of insufficiency of optical system, i.e., insufficiency of mainly perpendicularity of an optical axis of an illumination light of the overlay metrology system. If the TIS is larger, even when the same measurement mark is measured, an error of a measured value of overlay accuracy becomes large. That is, accuracy of the overlay metrology system is low.
When elements of semiconductor devices and LCDs are manufactured, overlay deviation occurs among the elements due to the following causes:
(A) An aligner has an error in exposure position setting; PA1 (B) When elements are formed by using a plurality of steppers through a plurality of processes, lenses of the steppers have a lens distortion difference; PA1 (C) A semiconductor substrate is contracted by heat; and PA1 (D) A pattern is transferred under the condition that the semiconductor substrate is rotated (i.e., so-called chip rotation occurs).
Further, an apparent overlay deviation of elements is caused by the overlay metrology system. In the SEM type overlay metrology system and the optical type overlay metrology system, the apparent overlay deviation is caused by:
(a) focus position of the overlay metrology system. Furthermore, in the optical type overlay metrology system, the apparent overlay deviation occurs due to the following causes: PA2 (b) An image reading system when a measurement mark is read into the overlay metrology system as an image (e.g., bright field image, dark field image, interference image, scattered image); PA2 (c) Various optical system constants, such as a numerical aperture of lens, wavelength band of an illumination light or the like; PA2 (d) A difference of intensity; and PA2 (e) A distortion of an optical axis of an illumination light. A measurement error occurs in the overlay metrology system due to the aforesaid factors.
If the measurement conditions of the overlay metrology system are optimized, then the value of overlay deviation obtained by the overlay metrology system becomes close to a value of true overlay deviation amount. The true overlay deviation amount will be described with reference to FIGS. 2A through 2D. FIGS. 2A through 2D are fragmentary cross-sectional views schematically showing a semiconductor device, by way of example.
As shown in FIG. 2A, an interlevel insulator 102 made of SiO.sub.2 is formed on a semiconductor substrate 100 by a CVD (chemical vapor deposition) method, and a contact hole 102 is formed through the interlevel insulator 102 by a RIE (reactive ion etching) method. Then, in order to form a wiring layer made of an aluminum at the central portion of the contact hole 104, an aluminum thin film layer 106 is formed on the whole surface by a sputtering method, for example (see FIG. 2B).
Then, a resist layer 110 formed as a pattern by a photolithography method is formed on the aluminum thin film layer 106 (see FIG. 2C). At that time, the aluminum thin film layers 106 formed on the stepped portions of the interlevel insulator 102 become asymmetrical coverages. A.sub.1 and B.sub.1 assume distances from stepped portions 108A, 108B of the aluminum thin film layer 106 to the resist layer 100, respectively.
Subsequently, the aluminum thin film layer 106 is etched away by using the resist layer 110 formed as the pattern to thereby eliminate the resist layer 110. In this way, there is obtained a semiconductor device having a structure shown in FIG. 2D. A.sub.2 and B.sub.2 assume distances from stepped portions 102A, 102B of the interlevel insulator 102 to the aluminum thin film layer 106A (wiring layer) formed as the pattern. In this case, since the aluminum thin film layer 106 is made asymmetrical by the stepped portions 102A, 102B of the interlevel insulator 102, a value of (A.sub.1 -B.sub.1)/2 and a value of (A.sub.2 -B.sub.2)/2 are different. That is, we have: EQU (A.sub.1 -B.sub.1)/2 (A.sub.2 -B.sub.2)/2
The value of (A.sub.1 -B.sub.1)/2 and the value of (A.sub.2 -B.sub.2)/2 are referred to as overlay deviation amounts. Also, the value of (A.sub.2 -B.sub.2)/2 provided after the etching process is referred to as a true overlay deviation amount.
Since the aluminum thin film layer 106 is made asymmetrical by the stepped portions 102A and 102B of the interlevel insulator 102, we have: EQU (A.sub.1 -B.sub.1)/2 (A.sub.2 -B.sub.2)/2
Other causes are that incident angles of ions are asymmetrical when the aluminum thin film layer 106 is etched away and that the side walls of the resist layer 110 thus formed as the pattern are asymmetrical to each other.
When the true overlay deviation amount between the semiconductor device elements (e.g., the interlevel layer 102 and the wiring layer 106A in the above-mentioned example) in the semiconductor device after the etching process is larger than a predetermined value, a semiconductor apparatus becomes defective. Therefore, before the etching process, it must be determined whether or not the overlay deviation amount between the semiconductor device elements is larger than the predetermined value.
In the manufacturing process of semiconductor devices and LCDs, there is utilized an aligner of a step and repeat system. FIG. 3 schematically shows an example of an arrangement of the aligner of step and repeat type. The position of an exposure stage is controlled with accuracy by a laser interferometer. In order to etch the substrate with high accuracy by the aligner, the position of the substrate (or substrate stage) in the aligner must be controlled with high accuracy. To this end, a plurality of alignment marks are formed on the substrate in advance and the alignment marks are measured according to an alignment mark measurement system installed in the aligner. Then, the position of the substrate (or substrate stage) is controlled on the basis of measured results.
The aligner of the step and repeat system generally includes a plurality of alignment mark measurement systems. A plurality of alignment mark measurement systems may be formed of a plurality of hardwares or may be formed of a plurality of analytical algorithms (analytical algorithms for processing an output signal from a hardware) installed in one hardware.
In order to select the optimum alignment mark measurement system, i.e., in order to optimize these alignment mark measurement systems of the aligner, it is customary that alignment marks are measured by using various kinds of alignment mark measurement systems and the positions of the substrates are matched. Then, a photosensitive resin formed on the substrate is exposed and developed by the aligner to form a pattern in actual practice. Thereafter, a deviation of the position of the pattern formed by exposing and developing the photosensitive resin relative to the pattern of the under layer must be visually measured by using a vernier or the like or measured by the overlay metrology system. Then, the alignment mark measurement system which can produce the smallest deviation is selected.
The measurement reproducibility (3.sigma.) and TIS that are the accuracy standards of the overlay metrology system do not include all measurement errors caused when the overlay metrology system is applied to the actual semiconductor devices having coarse surfaces, stepped portions or the like.
There is not known a method of optimizing measurement conditions of the overlay metrology system in order to minimize a measurement error included by the overlay metrology system.
Also, there is not known a method of optimizing measurement conditions of the overlay metrology system in order to correlate the true overlay deviation amount among the semiconductor device elements in the semiconductor device after the etching process and the overlay deviation amount among the semiconductor device elements in the semiconductor device before the etching process.
Particularly, in the measurement of the overlay deviation amount among the semiconductor device elements in the semiconductor device before the etching process, a measurement error tends to occur because images of the semiconductor device elements obtained by the overlay metrology system are not clear generally. Accordingly, in the prior art, it is very difficult to reduce the measurement error inherent in the overlay metrology system as much as possible.
Furthermore, there is not known a method of optimizing measurement conditions of the overlay metrology system in consideration of the fact that the values of the overlay deviation amounts before and after the etching process caused by the asymmetry of the coverages of, for example, the aluminum thin film layer 106 are different as described above with reference to FIGS. 2A through 2D.
In the aligner of the step and repeat type, the optimum measurement system is selected from a plurality of alignment mark measurement systems. That is, the alignment mark measurement system must be optimized. When the alignment mark measurement system is formed of a plurality of hardwares, alignment evaluation substrates that are subjected to the overlay exposure process must be produced at every hardware. When the alignment mark measurement system is formed of a plurality of analytical algorithms installed on one hardware, the alignment evaluation substrates that are subjected to the overlay exposure must be produced further at every analytical algorithms. Then, the deviation of the pattern formed by exposing and developing the photosensitive resin on such alignment evaluation substrate relative to the pattern of the under layer is measured and the alignment mark measurement system having the smallest deviation is selected.
In order to determine the shape of the alignment mark best suited to a certain alignment mark measurement system, alignment marks having various shapes must be formed on the substrate.
Therefore, when the alignment mark measurement system is formed of a plurality of hardwares and is further formed of a plurality of analytical algorithms installed on one hardware, a number of alignment evaluation substrates must be produced on the basis of many conditions in order to select the optimum alignment mark measurement system or optimum shape of the alignment mark.
As earlier described, it is frequently observed that the values of the overlay deviations before and after the etching process are different due to the asymmetry of the aluminum thin film layer in the stepped portions of the interlevel insulator. From the device design standpoint, the value of the overlay deviation amount provided after the etching process indicates the true overlay deviation amount. Therefore, when the values of the overlay deviation amounts before and after the etching process are different, the alignment mark measurement system is comprised of a plurality of hardwares and when the alignment mark measurement system is comprised of a plurality of analytical algorithms, after a number of alignment evaluation substrates are produced, the deviation of the pattern formed on the alignment evaluation substrate relative to the alignment mark is measured. Then, the etching is carried out, whereafter the true overlay deviation amount of the alignment evaluation sample must be measured by the overlay metrology system.
Therefore, a number of alignment evaluation substrates must be produced in consideration of many conditions. Also, after the etching process, the overlay deviation amounts must be measured. There is then the problem that a number of substrates and a number of processes are required. In addition, the measurement of the overlay deviation after the etching process contains a measurement error caused when the alignment measurement system is not optimized and a measurement error inherent in the overlay metrology system. These two types of measurement errors cannot be discriminated substantially.